This application claims the priority benefit of Taiwan application serial no. 90105104, filed Mar. 6, 2001.
1. Field of Invention
The present invention relates to a memory structure. More particularly, the present invention relates to a non-volatile memory structure having a high gate-coupling ratio.
2. Description of Related Art
In integrated circuit applications, erasable and programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory are commonly used non-volatile memories. Each of these non-volatile memories utilizes the application of a positive or a negative voltage to its control gate to control the injection of charges into the floating gate or the removal of charges from the floating gate. Data is stored as electric charges inside the memories. Hence, data is retained even if power source for driving the memory is cut.
In general, most gate structures of a non-volatile memory unit has a stacked gate design that includes a floating gate for holding electric charges, an oxide-nitride-oxide (ONO) structure serving as a dielectric layer and a control gate form controlling data access. The memory unit utilizes either hot carrier effect or tunneling effect to drive electric charges into the floating gate of the stacked gate structure so that a logic xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99 is represented. To change the data inside the memory, a reverse voltage is applied to the control gate so that the accumulated charges inside the floating gate are channeled away.
Among the conventional non-volatile memory structures, the so-called twin cell design is quite common. FIGS. 1A through 1D are schematic cross-sectional views showing the progression of steps for forming the stacked gate of a conventional twin cell non-volatile memory unit. As shown in FIG. 1A, a semiconductor chip 10 that includes a silicon substrate 12 is provided. A pair of shallow trench isolation (STI) structures 14 are formed in the substrate 12. A thermal oxidation layer (not shown), a polysilicon layer (not shown) and a silicon nitride layer (not shown) are sequentially formed over the silicon substrate 12. After performing a photolithographic and etching process, a pair of tunnel oxide layers 16, a pair of polysilicon layers 18 and a pair of silicon nitride layer 20 are formed.
As shown in FIG. 1B, an ion implantation of the substrate 12 is conducted while using the silicon nitride layer 20 and the pair of STI layers 14 as a mask. A high-temperature oxidation treatment is carried out to activate the doped ions, thereby forming a pair of ion-doped layers 22 at a pre-determined depth to serve as a drain terminal and a source terminal, respectively. In the meantime, a thermal oxidation layer 24 is formed over each ion-doped layer 22. Hence, one ion-doped layer 22 of the pair forms a buried drain (BD) while the other ion-doped layer 22 forms a buried source (BS) respectively.
As shown in FIG. 1C, the silicon nitride layer 20 is completely removed. A pair of polysilicon layers 26 are formed in pre-defined regions above the semiconductor chip 10. Each polysilicon layer 18 and its overlying polysilicon layer 26 together form a floating gate 28 of the non-volatile memory unit.
As shown in FIG. 1D, an oxide-nitride-oxide (ONO) structure, serving as a dielectric layer 30, is formed over the silicon substrate 12. The ONO structure is a composite layer. Finally, a control gate 32 is formed over the silicon substrate 12. The control gate 32 covers the dielectric layer 30 within the pre-defined regions and the thermal oxidation layers 24.
The floating gate 28, the dielectric layer 30 and the control gate 32 together form the stacked gate 34 of a non-volatile memory unit. The pair of floating gates 28 between the pair of field oxide layer is a pair of storage units of the twin-cell structure. When a high voltage is applied to the control gate 32 of the stacked gate 34, carrier multiplication occurs at the junction between the drain terminal 22 and the silicon substrate 12 leading to the generation of hot electrons. A portion of the hot electrons is driven past the tunnel oxide layer 16 into the floating gate 28 so that the floating gate 28 is negatively charged. Such negative charges are trapped inside the floating gate 28 due to the surrounding dielectric layer 30 and the tunnel oxide layer 16. This completes a data input operation.
Because the conventional process uses a high-temperature oxidation step to form the thermal oxide layers 24, a bird""s beak structure is formed at each end of the thermal oxide layer 24. This leads to a variation of thickness in the thermal oxidation layer 24 in addition to lattice structure damages near the surface of the silicon substrate 12. Ultimately, reliability of the twin-cell unit is greatly affected. Furthermore, dimensions of a device are severely limited by the thermally formed oxide layer 24.
In addition, the high-temperature process may also over-drive ions into the drain terminal and the source terminal 22, leading to a shortening of channel length underneath the tunnel oxide layer 16. This will increase the frequency of punchthrough between the drain terminal and the source terminal. Consequently, electrical properties of the twin-cell unit may be severely affected, resulting in a lowering of the yield rate in the production process.
Accordingly, one object of the present invention is to provide a non-volatile memory structure having a higher gate-coupling ratio. The structure includes a substrate having a pair of shallow trench isolation (STI) layers, a pair of tunnel oxide layers, a pair of buried source/drain regions, a first dielectric layer, a pair of floating gates, a second dielectric layer and a control gate. The pair of tunnel oxide layers is formed on the upper surface of the substrate between the STI layers. The buried source/drain regions are formed within the substrate between the STI layers and the tunnel oxide layers. The first dielectric layer is formed above the substrate covering the buried source/drain regions. The first dielectric layer has an opening above each of the tunnel oxide layers. Each floating gate comprises a first polysilicon layer and a second polysilicon layer. The first polysilicon layer is embedded within the opening. The second polysilicon layer is formed over a portion of the first polysilicon layer and is electrically connected with the first polysilicon layer. The second dielectric layer is formed on the upper surface of the floating gate and the control gate is formed over the second dielectric layer.
Instead of forming a thermally grown oxide layer, the dielectric layer deposited around the first polysilicon layer serves as an insulation layer above the buried source/drain regions. Hence, unevenness of the insulation layer above the buried source/drain region is prevented. In addition, thickness of the buried source/drain regions and channel length underneath each stacked gate in each semiconductor chip can be accurately controlled. Consequently, reliability problems caused by device miniaturization can be avoided.
Furthermore, the opening in the dielectric layer creates a concave three-dimensional structure for the floating gate so that a subsequently formed control gate can have a greater contact area. Hence, the gate-coupling ratio (GCR) of the semiconductor device is increased and ultimately the electrical characteristic of the semiconductor product is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.